1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit in accordance with the technology of the present invention may include a semiconductor memory, such as a Dynamic Random Access Memory (DRAM).
FIG. 1 is a block view showing a conventional Double Data Rate 3 Dynamic Random Access Memory (DDR3 DRAM) device, which uses an external power supply voltage and an internal power supply voltage.
Referring to FIG. 1, the DDR3 DRAM device 10 includes a power supply voltage pad 12, a voltage booster 14, and an internal circuit 16. The power supply voltage pad 12 receives a power supply voltage VDD from the outside. The voltage booster 14 boosts the power supply voltage VDD applied through the power supply voltage pad 12 to generate a boosted voltage VPP whose voltage level is higher than that of the power supply voltage VDD. The internal circuit 16 performs assigned operations based on the power supply voltage VDD and the boosted voltage VPP.
FIG. 2 is a block view showing a conventional DDR4 DRAM device, which uses an external power supply voltage and an internal power supply voltage.
Referring to FIG. 2, the DDR4 DRAM device 20 includes a power supply voltage pad 22, a voltage booster pad 24, and an internal circuit 26. The power supply voltage pad 22 receives a power supply voltage VDD from the outside. The voltage booster pad 24 receives a boosted voltage VPP whose voltage level is higher than that of the power supply voltage VDD from the outside. The internal circuit 26 performs assigned operations based on the power supply voltage VDD and the boosted voltage VPP that are received through the power supply voltage pad 22 and the voltage booster pad 24. In short, the DDR4 DRAM device 20 may not include the voltage booster 14 for a normal operation, compared with the DDR3 DRAM device 10.
The DDR4 DRAM device 20, however, is to receive both the power supply voltage VDD and the boosted voltage VPP from the outside even in a test mode, just as in a normal mode. This is because the DDR4 DRAM device 20 does not include a voltage booster for generating the boosted voltage VPP. For this reason, a probe test device allocates channels to the power supply voltage pad 22 and the voltage booster pad 24 of the DDR4 DRAM device 20 in order to supply the power supply voltage VDD and the boosted voltage VPP in the test mode. The allocation of channels for those pads means electrical connection with the probe test device to receive a corresponding power supply and a signal from the probe test device. Since the DDR4 DRAM device 20 has an increased number of pads 22 and 24 to which channels are allocated, the number of DRAM devices to be tested simultaneously in the test mode is decreased. Therefore, production cost and time may increase to perform test operations.